PAGE
STANDARD
NAME
RS
RD/
DB0-DB7
tRSS
tf
tRSH
tr
tRDL
tRDH
tDHRi
tCYCRD
tDDi
Figure 6.
Intel I80-Type Parallel Interface Read Cycle Timing
3.7.4 SYNCHRONOUS SERIAL INTERFACE TIMING
(See Figures 7, 8 and 12)
Item
Symbol
Min.
Max.
Unit
STB setup time
tSTBS
100
-
ns
STB hold time
tSTBH
500
-
ns
Input signal fall time
tf
-
15
ns
Input signal rise time
tr
-
15
ns
STB pulse width high
tWSTB
500
-
ns
SCK pulse width high
tSCKH
200
-
ns
SCK pulse width low
tSCKL
200
-
ns
SI data setup time
tDSs
100
-
ns
SI data hold time
tDHs
100
-
ns
SCK cycle time
tCYCSCK
500
-
ns
SCK wait time between bytes
tWAIT
1
-
us
SO data delay time
tDDs
-
150
ns
SO data hold time
tDHRs
5
-
ns
Note: All timing is specified using 20% and 80% of VCC
as the reference points.
10/24
REV. NO.
03
DOCUMENT NO.